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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDECR, External Debug Execution Control Register</h1><p>The EDECR characteristics are:</p><h2>Purpose</h2>
        <p>Controls Halting debug events.</p>
      <h2>Configuration</h2><p>When FEAT_DoPD is implemented, EDECR is in the Core power domain. Otherwise, EDECR is in the Debug power domain.
    </p><h2>Attributes</h2>
        <p>EDECR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="25"><a href="#fieldset_0-31_7">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6-1">TRBE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-5_5-1">TRCE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4-1">PME</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">SS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1-1">RCE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0-1">OSUCE</a></td></tr></tbody></table><h4 id="fieldset_0-31_7">Bits [31:7]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-6_6-1">TRBE, bit [6]<span class="condition"><br/>When FEAT_Debugv8p9 is implemented and FEAT_TRBE_EXT is implemented:
                        </span></h4><div class="field">
      <p>Trace Buffer External Debug Request Enable.</p>
    <table class="valuetable"><tr><th>TRBE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Trace Buffer External Debug Request disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trace Buffer External Debug Request enabled.</p>
        </td></tr></table>
      <p>This field is in the Core power domain.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-6_6-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-5_5-1">TRCE, bit [5]<span class="condition"><br/>When FEAT_ETEv1p3 is implemented and FEAT_Debugv8p9 is implemented:
                        </span></h4><div class="field">
      <p>ETE External Debug Request Enable.</p>
    <table class="valuetable"><tr><th>TRCE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>ETE External Debug Request disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>ETE External Debug Request enabled.</p>
        </td></tr></table>
      <p>This field is in the Core power domain.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-5_5-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4-1">PME, bit [4]<span class="condition"><br/>When FEAT_Debugv8p9 is implemented and FEAT_PMUv3p9 is implemented:
                        </span></h4><div class="field">
      <p>PMU Overflow External Debug Request Enable.</p>
    <table class="valuetable"><tr><th>PME</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU Overflow External Debug Request disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU Overflow External Debug Request enabled.</p>
        </td></tr></table>
      <p>This field is in the Core power domain.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-4_4-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-3_3">Bit [3]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-2_2">SS, bit [2]</h4><div class="field">
      <p>Halting step enable. Possible values of this field are:</p>
    <table class="valuetable"><tr><th>SS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Halting step debug event disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Halting step debug event enabled.</p>
        </td></tr></table>
      <p>If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> as described in <span class="xref">'Changing the value of EDECR.SS when not in Debug state'</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, when FEAT_DoPD is implemented, 
      this field resets
       to <span class="binarynumber">0</span>.
</li><li>On an External debug reset, when FEAT_DoPD is not implemented, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-1_1-1">RCE, bit [1]<span class="condition"><br/>When FEAT_DoPD is not implemented:
                        </span></h4><div class="field">
      <p>Reset Catch Enable.</p>
    <table class="valuetable"><tr><th>RCE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Reset Catch debug event disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Reset Catch debug event enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On an External debug reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-1_1-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0-1">OSUCE, bit [0]<span class="condition"><br/>When FEAT_DoPD is not implemented:
                        </span></h4><div class="field">
      <p>OS Unlock Catch Enable.</p>
    <table class="valuetable"><tr><th>OSUCE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>OS Unlock Catch debug event disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>OS Unlock Catch debug event enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On an External debug reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-0_0-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h2>Accessing EDECR</h2><h4>EDECR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>Debug</td><td><span class="hexnumber">0x024</span></td><td>EDECR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When (FEAT_DoPD is not implemented or IsCorePowered()) and SoftwareLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>When (FEAT_DoPD is not implemented or IsCorePowered()) and !SoftwareLockStatus(), accesses to this register are <span class="access_level">RW</span>.
          </li><li>Otherwise, accesses to this register generate an error response.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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